The present invention relates to electronic semiconductor devices and methods of fabrication, and more specifically, to semiconductor memory devices such as static random access memories.
Static random access memories (SRAMS) having memory cells which incorporate two conventional cross-coupled CMOS inverters are particularly useful in applications such as communication satellites where minimal power consumption is a requirement. As will be described more fully below, the power saving advantage of this cell is frequently diminished by a period of high current drain upon the application of power to the memory circuit.
An understanding of the structure and operation of a static memory cell which may exhibit increased power consumption during power-up is best described with reference to FIG. 1 which illustrates a schematic drawing of a conventional CMOS (complementary metal oxide semiconductor) static memory cell as typically used in a static random access memory (SRAM). Memory cell 2 is constructed using well known methods of cross-coupled CMOS inverter fabrication (see, for example, Muller and Kamins, "Device Electronics for Integrated Circuits", Second Edition, 1986, pp. 449-467). A first CMOS inverter 4 in memory cell 2 is comprised of P-channel transistor 6 and N-channel transistor 8 each having source-to-drain paths which are connected in series between a source of supply voltage Vcc and a reference node such as ground. The gate electrodes of transistors 6 and 8 are connected in common. The second CMOS inverter 5 in memory cell 2 is similarily constructed, with P-channel transistor 10 and N-channel transistor 12 each having source-to-drain paths which are connected in series between Vcc and ground. The gate electrodes of transistors 10 and 12 are also connected in common. The cross-coupling connections are accomplished by connecting the gate electrodes of transistor 6 and 8 to the drains of transistors 10 and 12 (node S2), and by connecting the gate electrodes of transistors 10 and 12 to the drains of transistors 6 and 8 (node S1). N-channel pass transistor 14 has a source-to-drain path coupled between node S1 and a first bit line BL and pass transistor 16 has a source-to-drain path coupled between node S2 and a second bit lin BL . The gate electrodes of both transistors 14 and 16 are connected to a word line WL. Pass transistors 14 and 16, when enabled, allow data to transfer into and out of the memory cell 2 from bit lines BL and BL.sub.- respectively. Pass transistors 14 and 16 are enabled by a signal on word line WL which is provided by decoding a row address applied to the SRAM and decoded by a row decoder in the SRAM (not shown). The decode function enables one out of n word lines where n is the number of rows of memory cells in the SRAM.
In operation, the stable state voltages on nodes S1 and S2 will necessarily be the logical complements of one another as a result of the cross-coupled configuration of inverters 4 and 5. When pass transistors 14 and 16 turn on by application of an appropriate signal to word line WL, nodes S1 and S2 are respectively coupled to bit lines BL and BL.sub.-. Accordingly, the state of the cell may be determined by enabling word line WL to establish a voltage differential between bit lines BL and BL.sub.- which may be appropriately sensed in a read operation. Alternatively, peripheral circuitry may be activated to impress a voltage on BL and BL.sub.- and alter the state of memory cell 2 to effect a write operation. The sizes of the transistors shown FIG. 1 are typically selected such that when pass transistors 14 and 16 are turned on by word line WL, a differentially low voltage at bit line BL with respect to bit line BL can force node S2 to a logic low level. However, the sizes of the transistors shown in Figure are also chosen such that when transistors 14 and 16 are on, a differentially high voltage at bit line BL with respect to bit line BL.sub.- will not force node S1 high. In addition, a differentially high voltage at bit line BL.sub.- with respect to bit line BL will not force node S2 high. As a result, writing to the memory cell is accomplished by forcing the desired bit line and the desired side of cell 2 at either node S1 or S2 to a logic low, which in turn causes the opposite side of cell 2 to have a logic high state.
As mentioned previously, an advantage of the above cell arrangement is low power consumption. In a stable state, nodes S1 and S2 remain at full and opposite logic levels. In this quiescent condition, one of the two transistors in each inverter 4 and 5 is non-conducting and there is no direct current path from the supply voltage except for perhaps junction leakages.
It has been observed, however, that upon the application of power to the memory circuit, it is possible for the CMOS memory cell of the type shown in FIG. 1 to experience a balanced condition in which the voltage at nodes S1 and S2 may be about equal and at a level that is between that of Vcc and ground. Under these conditions, the memory cell will experience high current conduction and unwanted power consumption as both the P-channel and the N-channel transistors of inverters 4 and 5 simultaneously conduct.
Static memory cells of the type described and operating in certain environments in which radiation is present such as communication satellite orbital space are particularly vulnerable to soft error mechanisms such as gamma dot or SEU (single event upset). Numerous methods have been proposed for reducing susceptibility to these mechanisms including the circuit of FIG. 2 which incorporates two depletion mode P-channel devices 18 and 20 in the cross-couple path of a device like that shown in FIG. 1 (See, for example, copending application Ser. No. 252,291, filed Sept. 30, 1988, assigned to Texas Instruments Incorporated Transistors 18 and 20 serve to inhibit nodes S2 and S1 from going to a high voltage from a low voltage in response to pulsed transient dose radiation by adding resistance to the cross-couple path and increasing the RC time constant delay. Upon the application of power to this circuit arrangement, the added delay will tend to increase the period of balanced operation resulting in increased dc current drain and power consumption.
Finally, at the system level, it is frequently useful to incorporate a memory device that provides a predetermined data pattern at the time power is applied to the system. A typical example of this is the storage of a "bootstrap program" which is a program executed automatically when, for example, a computer system is switched on. In the past, this is usually accomplished by providing a nonvolatile memory such as a ROM (read only memory such as PROM, EPROM, or EEPROM) which has been previously programmed and will not lose the program data when power to the system is interrupted. Such devices may be costly and, more importantly, may not be used for random memory purposes since the data sorted in these devices is intended to remain fixed during system operation.
Accordingly, it would be desirable to provide a memory cell that avoids the problem of increased power consumption upon application of power to the memory circuit. It would also be desirable to provide a memory device that may be configured to provide a predetermined data pattern (which may include resetting all memory cells to the same logic state) upon the application of power yet operate as a random access memory during normal system operation. It is therefore an object of the invention to provide a new and improved memory cell which may be incorporated into a high density integrated circuit. It is another object of the invention to provide a memory cell that exhibits reduced power consumption. It is yet a further object of the invention to provide a random access memory device that provides a fixed data pattern upon the application of power to the device. It is still a further object of the invention to provide a random access memory device that clears or resets upon the application of power to the device.